This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Images are for reference only,

See Technical Specifications

A3P400-FGG144 +BOM

LEAD FREE A3P400-FGG144 Field Programmable Gate Array FPGA

Manufacturer:

Microchip Technology
Mfr.Part #:

A3P400-FGG144
Datasheet:

A3P400-FGG144 Datasheet (PDF)
Series:

ProASIC3
Programmabe:

Not Verified
Total RAM Bits:

55296
Number Of I/O:

97
EDA/CAD Models:

Request Free CAD Models for A3P400-FGG144

A3P400-FGG144 General Description

Representing the cutting edge of FPGA technology, the A3P400-FGG144 is a versatile solution for medium complexity logic functions. Its 144-pin FBGA package houses a powerhouse of 400,000 system gates, offering a wide range of applications in industrial, automotive, communication, and consumer electronics sectors. The FPGA's robust security features, including advanced encryption and authentication, ensure the safety of critical data and prevent unauthorized access

Key Features

High Capacity
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†
FlashLock® to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os‡
Programmable Output Slew Rate† and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft Processor Available with or without Debug

Specifications

Series	ProASIC3	Programmabe	Not Verified
Total RAM Bits	55296	Number of I/O	97
Number of Gates	400000	Voltage - Supply	1.425V ~ 1.575V
Mounting Type	Surface Mount	Operating Temperature	0°C ~ 85°C (TJ)
Base Product Number	A3P400