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A3PE600L-FG484M +BOM
A3PE600L-FG484M FPGA
FBGA-
Manufacturer:
MICROCHIP TECHNOLOGY INC
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Mfr.Part #:
A3PE600L-FG484M
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Datasheet:
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Part Life Cycle Code:
Active
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Reach Compliance Code:
compliant
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ECCN Code:
3A001.A.2.C
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HTS Code:
8542.39.00.01
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EDA/CAD Models:
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Availability: 7072 PCS
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A3PE600L-FG484M General Description
In summary, the A3PE600L-FG484M is a cutting-edge FPGA that combines high performance with robust security features. Its extensive system gates, logic elements, and embedded block RAM make it a reliable choice for demanding designs, while its voltage options and IO standards support provide flexibility and ease of integration. Whether you're working on a medium-scale project or a high-density application, this FPGA offers the power and security you need for successful data processing
Key Features
- Military Temperature Tested and Qualified
- Each Device Tested from –55°C to 125°C
- Firm-Error Immune
- Not Susceptible to Neutron-Induced Configuration Loss
- Low Power
- Dramatic Reduction in Dynamic and Static Power
- 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power†
- Low Power Consumption in FlashFreeze Mode Allows for
- Instantaneous Entry To / Exit From Low-Power FlashFreeze
- Modeƒ
- Supports Single-Voltage System Operation
- Low-Impedance Switches
- High Capacity
- 600 k to 3 M System Gates
- Up to 504 kbits of True Dual-Port SRAM
- Up to 620 User I/Os
- Reprogrammable Flash Technology
- 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
- Live-at-Power-Up (LAPU) Level 0 Support
- Single-Chip Solution
- Retains Programmed Design when Powered Off
- High Performance
- 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
- Performance
- 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
- PCI (1.2 V systems)
- In-System Programming (ISP) and Security
- Secure ISP Using On-Chip 128-Bit Advanced Encryption
- Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
- FlashLock® to Secure FPGA Contents
- High-Performance Routing Hierarchy
- Segmented, Hierarchical Routing and Clock Structure
- High-Performance, Low-Skew Global Network
- Architecture Supports Ultra-High Utilization
Specifications
Part Life Cycle Code | Active | Reach Compliance Code | compliant |
ECCN Code | 3A001.A.2.C | HTS Code | 8542.39.00.01 |
Clock Frequency-Max | 250 MHz | JESD-30 Code | S-PBGA-B484 |
JESD-609 Code | e0 | Length | 23 mm |
Moisture Sensitivity Level | 3 | Number of CLBs | 13824 |
Number of Equivalent Gates | 600000 | Number of Inputs | 270 |
Number of Logic Cells | 13824 | Number of Outputs | 270 |
Number of Terminals | 484 | Operating Temperature-Max | 125 °C |
Operating Temperature-Min | -55 °C | Organization | 13824 CLBS, 600000 GATES |
Peak Reflow Temperature (Cel) | 225 | Power Supplies | 1.2/1.5,1.2/3.3 V |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | Qualification Status | Not Qualified |
Seated Height-Max | 2.44 mm | Supply Voltage-Max | 1.575 V |
Supply Voltage-Min | 1.14 V | Supply Voltage-Nom | 1.2 V |
Surface Mount | YES | Technology | CMOS |
Temperature Grade | MILITARY | Terminal Finish | TIN LEAD |
Terminal Form | BALL | Terminal Pitch | 1 mm |
Terminal Position | BOTTOM | Time@Peak Reflow Temperature-Max (s) | 20 |
Width | 23 mm |
Service Policies and Others
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[email protected]Shipping Method
AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.
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In Stock: 7,072
Minimum Order: 1
Qty. | Unit Price | Ext. Price |
---|---|---|
1+ | - | - |
The prices below are for reference only.
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