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See Technical Specifications

CDCDB800RSLR +BOM

8-output clock buffer for PCIe® Gen 1 to Gen 6

Manufacturer:

TI
Mfr.Part #:

CDCDB800RSLR
Datasheet:

CDCDB800RSLR Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
Family:

CDC
EDA/CAD Models:

Request Free CAD Models for CDCDB800RSLR

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

CDCDB800RSLR General Description

The CDCDB800RSLR is a high-performance clock buffer designed to meet the demanding requirements of modern data communication systems. With its 8 output LP-HCSL configuration, this buffer is capable of distributing the reference clock for a wide range of interfaces, including PCIe Gen 1-6, QPI, UPI, SAS, and SATA. This versatility makes it an ideal choice for applications requiring precise timing synchronization across multiple devices

Key Features

Robust electromagnetic interference
Dual-input voltage regulation
Self-recovering mechanism

Specifications

Source Content uid	CDCDB800RSLR	Pbfree Code	Yes
Part Life Cycle Code	Active	Reach Compliance Code	compliant
Family	CDC	Input Conditioning	DIFFERENTIAL
JESD-30 Code	S-XQCC-N48	JESD-609 Code	e4
Length	6 mm	Logic IC Type	LOW SKEW CLOCK DRIVER
Moisture Sensitivity Level	1	Number of Functions	1
Number of Inverted Outputs		Number of Terminals	48
Number of True Outputs	16	Operating Temperature-Max	105 °C
Operating Temperature-Min	-40 °C	Packing Method	TR
Peak Reflow Temperature (Cel)	260	Power Supply Current-Max (ICC)	9 mA
Prop. Delay@Nom-Sup	3 ns	Propagation Delay (tpd)	3 ns
Same Edge Skew-Max (tskwd)	0.05 ns	Seated Height-Max	1 mm
Supply Voltage-Max (Vsup)	3.6 V	Supply Voltage-Min (Vsup)	3 V
Supply Voltage-Nom (Vsup)	3.3 V	Surface Mount	YES
Terminal Finish	NICKEL PALLADIUM GOLD	Terminal Form	NO LEAD
Terminal Pitch	0.4 mm	Terminal Position	QUAD
Width	6 mm	fmax-Min	250 MHz