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See Technical Specifications

CDCDB803RSLR +BOM

8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses

Manufacturer:

TI
Mfr.Part #:

CDCDB803RSLR
Datasheet:

CDCDB803RSLR Datasheet (PDF)
Function:

Clock buffer, Differential
Additive RMS Jitter (typ) (fs):

38
Output Frequency (max) (MHz):

250
Number Of Outputs:

8
EDA/CAD Models:

Request Free CAD Models for CDCDB803RSLR

CDCDB803RSLR General Description

The CDCDB803RSLR is an exceptional 8-output LP-HCSL clock buffer that complies with the DB800ZL standard, making it an ideal choice for distributing the reference clock for various high-speed interfaces such as PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA. Its SMBus interface and eight output enable pins give you the flexibility to configure and control all eight outputs individually, ensuring precise and tailored clock distribution for your specific requirements. Moreover, as a DB800ZL derivative buffer, the CDCDB803RSLR not only meets but exceeds the system parameters outlined in the DB800ZL specification, guaranteeing exceptional performance and reliability. It also meets or exceeds the parameters in the DB2000Q specification, further underscoring its suitability for demanding applications. Packaged in a compact 6-mm × 6-mm, 48-pin VQFN package, the CDCDB803RSLR offers a space-efficient solution for your clock distribution needs

Key Features

Superior phase coherence
Precision clock synthesis
Low power consumption
Advanced frequency planning
SMBus address selection
Configurable output skew

Specifications

Function	Clock buffer, Differential	Additive RMS jitter (typ) (fs)	38
Output frequency (max) (MHz)	250	Number of outputs	8
Output supply voltage (V)	3.3	Core supply voltage (V)	3.3
Output skew (ps)	50	Features	1:8 fanout, DB800ZL compliant, Individual output enable control, OE# control, PCIe Gen 1-5 compliant, SMBus control
Operating temperature range (°C)	-40 to 105	Rating	Catalog
Output type	LP-HCSL	Input type	LP-HCSL