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CDCLVD110ARHBT +BOM

1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution

CDCLVD110ARHBT General Description

With its ability to distribute differential LVDS clock inputs with minimal skew, the CDCLVD110A clock driver stands out as a top-tier solution for clock distribution applications. Its programmable outputs, coupled with an advanced start-up circuit, provide users with a versatile and highly efficient tool for managing clock signals. The device's robust design allows it to operate reliably in a wide temperature range, making it a dependable choice for demanding environments

cdclvd110arhbt

Key Features

  • Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
  • Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
  • VCC Range: 2.5 V ±5%
  • Typical Signaling Rate Capability of Up to 1.1 GHz
  • Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
  • Full Rail-to-Rail Common-Mode Input Range
  • Receiver Input Threshold: ±100 mV
  • Available in 32-Pin LQFP and VQFN Package
  • Fail-Safe I/O-Pins for VDD = 0 V (Power Down)

Specifications

Function Differential Additive RMS jitter (typ) (fs) 111
Output frequency (max) (MHz) 1100 Number of outputs 10
Output supply voltage (V) 2.5 Core supply voltage (V) 2.5
Output skew (ps) 50 Features 1:10 fanout, Individual output enable control
Operating temperature range (°C) -40 to 85 Rating Catalog
Output type LVDS Input type LVDS
feature-maximum-operating-supply-voltage-v 2.625 feature-minimum-operating-supply-voltage-v 2.375
feature-packaging Tape and Reel feature-rad-hard
feature-pin-count 32 feature-cecc-qualified No
feature-esd-protection feature-escc-qualified
feature-military No feature-aec-qualified No
feature-aec-qualified-number feature-auto-motive No
feature-p-pap No feature-eccn-code EAR99
feature-svhc No feature-svhc-exceeds-threshold No

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Ratings and Reviews

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E
E**n 08/22/2022

Good quality like expected.

8

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