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See Technical Specifications

D720100AS1 +BOM

French Electronic Distributor since 1988

Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95
PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI
host controller core for high-speed signaling.
Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction.
Configurable number of downstream facing ports (2 to 5)
32-bit 33 MHz host interface compliant to PCI Specification release 2.2.
Supports PCI Mobile Design Guide Revision 1.1.
Supports PCI-Bus Power Management Interface Specification release 1.1.
PCI Bus bus-master access
System clock is generated by 30 MHz X’tal or 48 MHz clock input.
Operational registers direct-mapped to PCI memory space
Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation.
3.3 V power supply, PCI signal pins have 5 V tolerant circuit.