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125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface
QFNManufacturer:
Mfr.Part #:
DS32EL0124SQE/NOPB
Datasheet:
Protocols:
Catalog
Rating:
Catalog
Operating Temperature Range (°C):
-40 to 85
Feature-function:
Deserializer
EDA/CAD Models:
Please fill in the short form below and we will provide you the quotation immediately.
By utilizing a parallel LVDS interface, the DS32EL0124/DS32ELX0124 chipset effectively reduces the number of required FPGA I/O pins, minimizes board trace count, and mitigates electromagnetic interference concerns. This innovative design approach offers a practical solution for addressing the challenges associated with traditional single-ended wide bus interfaces
Protocols | Catalog | Rating | Catalog |
Operating temperature range (°C) | -40 to 85 | feature-function | Deserializer |
feature-number-of-drivers | 5 | feature-number-of-receivers | 2 |
feature-number-of-elements-per-chip | 2 | feature-transmission-data-rate-mbps | 3125 |
feature-maximum-propagation-delay-time-ns | feature-input-signal-type | CML|LVCMOS | |
feature-differential-input-low-threshold-voltage-v | feature-differential-input-high-threshold-voltage-v | ||
feature-maximum-differential-output-voltage-v | 0.31 | feature-maximum-input-current-ua | 40 |
feature-supplier-temperature-grade | feature-packaging | Tape and Reel | |
feature-rad-hard | feature-pin-count | 48 | |
feature-cecc-qualified | No | feature-esd-protection | |
feature-escc-qualified | feature-military | No | |
feature-aec-qualified | No | feature-aec-qualified-number | |
feature-auto-motive | No | feature-p-pap | No |
feature-eccn-code | EAR99 | feature-svhc | Yes |
feature-svhc-exceeds-threshold | No |
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AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.
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Qty. | Unit Price | Ext. Price |
---|---|---|
1+ | - | - |
The prices below are for reference only.
All bill of materials (BOM) can be sent via email to
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