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See Technical Specifications

EP1K50TI144-2N +BOM

High-performance CMOS technology is used in this Loadable PLD, ensuring reliable operation

Manufacturer:

Intel
Mfr.Part #:

EP1K50TI144-2N
Datasheet:

EP1K50TI144-2N Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Reach Compliance Code:

compliant
HTS Code:

8542.39.00.01
Clock Frequency-Max:

37.5 MHz
EDA/CAD Models:

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EP1K50TI144-2N General Description

One of the standout features of the EP1K50TI144-2N FPGA is its four phase-locked loops (PLLs) for precise clock management, ensuring reliable operation and synchronization of signals. Additionally, this FPGA supports a wide range of I/O standards, making it compatible with various external devices and peripherals. With a maximum core voltage of 1.5V, the EP1K50TI144-2N FPGA strikes a balance between performance and power efficiency

Specifications

Part Life Cycle Code	Obsolete	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Clock Frequency-Max	37.5 MHz
JESD-30 Code	S-PQFP-G144	JESD-609 Code	e3
Length	20 mm	Moisture Sensitivity Level	3
Number of I/O Lines	102	Number of Inputs	102
Number of Logic Cells	2880	Number of Outputs	102
Number of Terminals	144	Operating Temperature-Max	85 °C
Operating Temperature-Min	-40 °C	Organization	102 I/O
Output Function	MIXED	Programmable Logic Type	LOADABLE PLD
Propagation Delay	0.4 ns	Qualification Status	Not Qualified
Seated Height-Max	1.6 mm	Supply Voltage-Max	2.625 V
Supply Voltage-Min	2.375 V	Supply Voltage-Nom	2.5 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	INDUSTRIAL	Terminal Finish	MATTE TIN
Terminal Form	GULL WING	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Width	20 mm