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See Technical Specifications

EP2C8Q208C7N +BOM

8256-Cell Architecture

Manufacturer:

Intel
Mfr.Part #:

EP2C8Q208C7N
Datasheet:

EP2C8Q208C7N Datasheet (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
HTS Code:

8542.39.00.01
Additional Feature:

ALSO REQUIRES 3.3 SUPPLY
EDA/CAD Models:

Request Free CAD Models for EP2C8Q208C7N

Email: [email protected]

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EP2C8Q208C7N General Description

II. For those new to FPGA design, the EP2C8Q208C7N simplifies the learning process with its user-friendly power and clocking circuitry, alongside an on-board EPROM programmer for easy FPGA chip configuration. Furthermore, the board is equipped with onboard devices such as LED lights, switches, and a seven-segment display, catering to students and hobbyists looking to experiment with FPGA design. Additionally, the inclusion of dedicated JTAG debug interfaces ensures easy debugging of FPGA designs, making it a valuable tool for both learning and professional development

Specifications

Part Life Cycle Code	Active	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Additional Feature	ALSO REQUIRES 3.3 SUPPLY
Clock Frequency-Max	450 MHz	JESD-30 Code	S-PQFP-G208
JESD-609 Code	e3	Length	28 mm
Moisture Sensitivity Level	3	Number of CLBs	516
Number of Inputs	138	Number of Logic Cells	8256
Number of Outputs	130	Number of Terminals	208
Operating Temperature-Max	85 °C	Operating Temperature-Min
Organization	516 CLBS	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	4.1 mm
Supply Voltage-Max	1.25 V	Supply Voltage-Min	1.15 V
Supply Voltage-Nom	1.2 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	OTHER
Terminal Finish	MATTE TIN	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Width	28 mm