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See Technical Specifications

EP2S15F484C3N +BOM

90nm technology-based FPGA from the Stratix® II Family, capable of running at 816.99MHz and powered by 1.2V

Manufacturer:

Intel
Mfr.Part #:

EP2S15F484C3N
Datasheet:

EP2S15F484C3N Datasheet (PDF)
Programmabe:

Not Verified
Number Of LABs/CLBs:

780
Number Of Logic Elements/Cells:

15600
Total RAM Bits:

419328
EDA/CAD Models:

Request Free CAD Models for EP2S15F484C3N

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EP2S15F484C3N General Description

The EP2S15F484C3N is a FPGA Logic IC from the Stratix II series, offering 342 I/Os and advanced clock management capabilities with PLL and DLL support. With a 3.3V I/O supply voltage and operating temperature range of 0°C to +85°C, this Logic IC is designed to deliver reliable performance in diverse applications. Its FBGA logic case style and 484 pins ensure secure and efficient integration into various electronic designs. Moreover, this product is RoHS compliant, aligning with environmental standards for a sustainable future

Key Features

15,600 to 179,400 equivalent LEs New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters Up to 16 global clocks with 24 clocking resources per device region Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting Support for numerous single-ended and differential I/O standards High-speed differential I/O support with DPA circuitry for 1-Gbps performance Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4 Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions Support for design security using configuration bitstream encryption Support for remote configuration updates

Specifications

Programmabe	Not Verified	Number of LABs/CLBs	780
Number of Logic Elements/Cells	15600	Total RAM Bits	419328
Number of I/O	342	Number of Gates	-
Voltage - Supply	1.15V ~ 1.25V	Mounting Type	Surface Mount
Operating Temperature	0°C ~ 85°C (TJ)