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See Technical Specifications

EP2S180F1508C4N +BOM

EP2S180F1508C4N is an FPGA from the Stratix II family, featuring 179400 cells and operating at a frequency of 711.24MHz

Manufacturer:

Altera
Mfr.Part #:

EP2S180F1508C4N
Datasheet:

EP2S180F1508C4N Datasheet (PDF)
Programmabe:

Not Verified
Number Of LABs/CLBs:

8970
Number Of Logic Elements/Cells:

179400
Total RAM Bits:

9383040

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

EP2S180F1508C4N General Description

In addition to its impressive technical specifications, the EP2S180F1508C4N comes in a convenient 780-pin FineLine BGA (FLBGA) package, ensuring easy integration into electronic systems without compromising on performance. Moreover, this FPGA supports various configuration methods, including using a serial configuration device or configuring through the JTAG interface, providing flexibility and ease of use for developers

Key Features

The Stratix II family offers the following
features:
15,600 to 179,400 equivalent LEs; see Table 1–1
New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency
Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources
TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers
High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
Up to 16 global clocks with 24 clocking resources per device region
Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
Support for numerous single-ended and differential I/O standards
High-speed differential I/O support with DPA circuitry for 1-Gbps performance
Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4
Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions
Support for design security using configuration bitstream encryption
Support for remote configuration updates

Specifications

Programmabe	Not Verified	Number of LABs/CLBs	8970
Number of Logic Elements/Cells	179400	Total RAM Bits	9383040
Number of I/O	1170	Number of Gates	-
Voltage - Supply	1.15V ~ 1.25V	Mounting Type	Surface Mount
Operating Temperature	0°C ~ 85°C (TJ)