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EPM9320LC84-15 +BOM

Discontinued Surface Mount RoHS Compliant Contains Lead CPLD 70C 5.25V 106mA 144MHz

Manufacturer:

Intel
Mfr.Part #:

EPM9320LC84-15
Datasheet:

EPM9320LC84-15 Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Reach Compliance Code:

compliant
HTS Code:

8542.39.00.01
Additional Feature:

484 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
EDA/CAD Models:

Request Free CAD Models for EPM9320LC84-15

EPM9320LC84-15 General Description

The EPM9320LC84-15, a state-of-the-art programmable logic device by Altera Corporation, is a key component in the MAX 9000 family of CPLD chips. Featuring 920 logic elements that can be programmed for various functions, this enhanced version of the PLD is housed in an 84-pin LCC package with up to 68 user I/O pins, ensuring versatile connectivity options. With a maximum propagation delay of 15ns, the EPM9320LC84-15 is designed for applications requiring medium to high-density logic implementation, such as telecommunications, networking, industrial automation, and automotive systems. Its reprogrammable and re-configurable features make it an invaluable tool for engineers seeking a reliable solution for prototyping and testing complex logic implementations

Key Features

It has an internal voltage regulator for stable supply voltages
- Includes a set of built-in digital signal processing blocks
- Built-in IEEE Std 1149.1 JTAG interface for in-system programming

Application

Streamlined solution for complex tasks
Seamless integration in any system
Enhanced features for exceptional performance

Specifications

Part Life Cycle Code	Obsolete	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Additional Feature	484 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
Clock Frequency-Max	117.6 MHz	In-System Programmable	YES
JESD-30 Code	S-PQCC-J84	JESD-609 Code	e0
JTAG BST	YES	Length	29.3116 mm
Moisture Sensitivity Level	3	Number of Dedicated Inputs
Number of I/O Lines	60	Number of Macro Cells	320
Number of Terminals	84	Operating Temperature-Max	70 °C
Operating Temperature-Min		Organization	0 DEDICATED INPUTS, 60 I/O
Output Function	MACROCELL	Programmable Logic Type	EE PLD
Propagation Delay	16 ns	Qualification Status	Not Qualified
Seated Height-Max	5.08 mm	Supply Voltage-Max	5.25 V
Supply Voltage-Min	4.75 V	Supply Voltage-Nom	5 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	COMMERCIAL	Terminal Finish	TIN LEAD
Terminal Form	J BEND	Terminal Pitch	1.27 mm
Terminal Position	QUAD	Width	29.3116 mm