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JM38510/66302BEA +BOM

Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-CDIP

Manufacturer:

Texas Instruments
Mfr.Part #:

JM38510/66302BEA
Datasheet:

JM38510/66302BEA Datasheet (PDF)
Series:

54HC
Logic Type:

Binary Counter
Direction:

Up
Number Of Elements:

1
EDA/CAD Models:

Request Free CAD Models for JM38510/66302BEA

JM38510/66302BEA General Description

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The HC161 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.

These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function for the HC161 devices is asynchronous. A low level at the clear (CLR)\ input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD)\, or enable inputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with Q_A high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Key Features

Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 14 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable

Specifications

Series	54HC	Logic Type	Binary Counter
Direction	Up	Number of Elements	1
Number of Bits per Element	4	Reset	Asynchronous
Timing	Synchronous	Count Rate	44 MHz
Trigger Type	Positive Edge	Voltage - Supply	2 V ~ 6 V
Operating Temperature	-55°C ~ 125°C (TA)	Mounting Type	Through Hole
Base Product Number	JM38510