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See Technical Specifications

KS8995XA +BOM

Ethernet LAN switching circuit featuring CMOS technology and a PQFP128 plastic package for enhanced durability

Manufacturer:

MICROCHIP
Mfr.Part #:

KS8995XA
Datasheet:

KS8995XA Datasheet (PDF)
Pbfree Code:

No
Part Life Cycle Code:

Obsolete
Pin Count:

128
Reach Compliance Code:

not_compliant
EDA/CAD Models:

Request Free CAD Models for KS8995XA

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

KS8995XA General Description

In terms of management, the KS8995XA offers various interfaces including a serial interface and an MDIO interface for easy configuration and monitoring. This makes it simple for network administrators to keep tabs on network activity and make any necessary adjustments. With built-in diagnostic tools, troubleshooting network issues is a breeze, ensuring minimal downtime and maximum efficiency

Key Features

Integrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard
Shared memory based switch fabric with fully nonblocking configuration
10BASE-T, 100BASE-TX and 100BASE-FX modes (FX in Ports 4 and 5)
Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII)
VLAN ID tag/untag options, per-port basis
Enable/disable option for huge frame size up to 1916 bytes per frame
Broadcast storm protection with percent control – global and per-port basis
Optimization for fiber-to-copper media conversion
Full-chip hardware power-down support (register configuration not saved)
Per-port-based software power-save on PHY (idle link detection, register configuration preserved)
QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ-based
802.1p/q tag insertion or removal on a per-port basis (egress)
Port-based VLAN support
MDC and MDI/O interface support to access the MII PHY control registers (not all control registers)
MII local loopback support
On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table)
1.4Gbps high performance memory bandwidth
Wire-speed reception and transmission
Integrated look-up engine with dedicated 1K unicast MAC addresses
Automatic address learning, address aging and address migration
Full-duplex IEEE 802.3x and half-duplex back pressure flow control
Comprehensive LED support
7-wire SNI support for legacy MAC interface
Automatic MDI/MDI-X crossover for plug-and-play
Disable automatic MDI/MDI-X option
Low power
Core: 1.8V
Digital I/O: 3.3V
Analog I/O: 2.5 or 3.3V
0.18µm CMOS technology
Commercial temperature range: 0°C to +70°C
Available in 128-pin PQFP package

Specifications

Source Content uid	KS8995XA	Pbfree Code	No
Part Life Cycle Code	Obsolete	Pin Count	128
Reach Compliance Code	not_compliant	HTS Code	8542.39.00.01
JESD-30 Code	R-PQFP-G128	JESD-609 Code	e0
Length	20 mm	Moisture Sensitivity Level	3
Number of Functions	1	Number of Terminals	128
Operating Temperature-Max	70 °C	Operating Temperature-Min
Peak Reflow Temperature (Cel)	240	Qualification Status	Not Qualified
Seated Height-Max	3.4 mm	Supply Voltage-Nom	1.8 V
Surface Mount	YES	Technology	CMOS
Telecom IC Type	LAN SWITCHING CIRCUIT	Temperature Grade	COMMERCIAL
Terminal Finish	Tin/Lead (Sn85Pb15)	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30	Width	14 mm