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See Technical Specifications

ORT8850L-2BMN680C +BOM

Advanced digital signal processing and computing capabilities for data-rich system

Manufacturer:

LATTICE SEMICONDUCTOR CORP
Mfr.Part #:

ORT8850L-2BMN680C
Datasheet:

ORT8850L-2BMN680C Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

680
Reach Compliance Code:

not_compliant
HTS Code:

8542.39.00.01
EDA/CAD Models:

Request Free CAD Models for ORT8850L-2BMN680C

ORT8850L-2BMN680C General Description

The ORT8850L-2BMN680C is a top-tier voltage regulator module defined by exceptional precision and compactness. With an input voltage range of 4.5V to 18V and an adjustable output voltage range of 0.8V to 5V, this module is suitable for a variety of power supply applications. Its maximum output current of 2A allows for effective powering of a diverse range of electronic devices and systems

Key Features

Embedded Core Features
Implemented in an ORCA Series 4 FPGA.
Allows a wide range of high-speed backplane applications, including SONET transport and termination.
No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz—106 MHz clock, and a frame pulse.
High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8 Gbits/s (full duplex).
HSI function uses Lattice’s 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are supported.
LVDS I/Os compliant with EIA®-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes.
Low-power 1.5 V HSI core.
Low-power LVDS buffers.
Programmable STS-3, and STS-12 framing.
Independent STS-3, and STS-12 data streams per quad channels.
8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic.
On-chip, Phase-Lock Loop (PLL) clock meets (type B) jitter tolerance specification of ITU-T recommendation G.958.
Powerdown option of HSI receiver on a per-channel basis.
HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.
Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above rates.
In-band management and configuration through transport overhead extraction/insertion.
Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted.
Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.
Built-in boundry scan (IEEE ®1149.1 JTAG).
FIFOs align incoming data across all eight channels (two groups of four channels or four groups of two channels) for both SONET scrambling. Optional ability to bypass alignment FIFOs.
1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications. STS-192 and above rates are supported through multiple devices.
ORCA FPGA soft intellectual property core support for a variety of applications.
Programmable Synchronous Transport Module (STM) pointer mover bypass mode.
Programmable STM framer bypass mode.
Programmable Clock and Data Recovery (CDR) bypass mode (clocked LVDS High-Speed Interface).
Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels with redundancy on a single device.

LATTICE SEMICONDUCTOR CORP Original Stock

Specifications

Part Life Cycle Code	Obsolete	Pin Count	680
Reach Compliance Code	not_compliant	HTS Code	8542.39.00.01
Additional Feature	SYSTEM GATES AVAILABLE UPTO 397000	Clock Frequency-Max	106.25 MHz
JESD-30 Code	S-PBGA-B680	JESD-609 Code	e1
Length	35 mm	Moisture Sensitivity Level	3
Number of Equivalent Gates	201000	Number of Terminals	680
Operating Temperature-Max	70 °C	Operating Temperature-Min
Organization	201000 GATES	Peak Reflow Temperature (Cel)	250
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	2.51 mm	Supply Voltage-Max	1.575 V
Supply Voltage-Min	1.425 V	Supply Voltage-Nom	1.5 V
Surface Mount	YES	Temperature Grade	COMMERCIAL
Terminal Finish	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Terminal Form	BALL
Terminal Pitch	1 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	40	Width	35 mm
Series	ORCA® 4	Programmabe	Not Verified
Number of Logic Elements/Cells	4992	Total RAM Bits	75776
Number of I/O	278	Number of Gates	397000
Voltage - Supply	1.425V ~ 3.6V	Mounting Type	Surface Mount
Operating Temperature	0°C ~ 70°C (TA)	Base Product Number	ORT8850