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See Technical Specifications

SC26C92A1A +BOM

Serial controller chip

Manufacturer:

PHILIPS SEMICONDUCTORS
Mfr.Part #:

SC26C92A1A
Datasheet:

SC26C92A1A Datasheet (PDF)
Part Life Cycle Code:

Transferred
HTS Code:

8542.31.00.01
JESD-30 Code:

S-PQCC-J44
JESD-609 Code:

e0

SC26C92A1A General Description

The SC26C92A1A is a versatile UART chip that offers high-speed serial communication capabilities for embedded systems. With two independent UART channels and a programmable baud rate of up to 1.5 Mbps, this chip is ideal for applications requiring fast and reliable data transfer. The 16-byte FIFO buffer ensures efficient data handling for both transmit and receive operations, while supporting a range of data formats and parity options for flexibility

Key Features

Dual full-duplex independent asynchronous receiver/transmitters
8 character FIFOs for each receiver and transmitter
Programmable data format
– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
16-bit programmable Counter/Timer
Programmable baud rate for each receiver and transmitter selectable from:
– 27 fixed rates: 50 to 230.4k baud
– Other baud rates to 230.4k baud at 16X
– Programmable user-defined rates derived from a programmable counter/timer
– External 1X or 16X clock
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
Programmable channel mode
– Normal (full-duplex)
– Automatic echo
– Local loopback
– Remote loopback
– Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
Multi-function 7-bit input port
– Can serve as clock, modem, or control inputs
– Change of state detection on four inputs
– Inputs have typically>100k pull-up resistors
Multi-function 8-bit output port
– Individual bit set/reset capability
– Outputs can be programmed to be status/interrupt signals
– FIFO states for DMA and modem interface
Versatile interrupt system
– Single interrupt output with eight maskable interrupting conditions
– Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
– Each FIFO can be programmed for four different interrupt levels
– Watch dog timer for each receiver
Maximum data transfer rates: 1X – 1Mb/sec, 16X – 1Mb/sec
Automatic wake-up mode for multidrop applications
Start-end break interrupt/status
Detects break which originates in the middle of a character
On-chip crystal oscillator
Power down mode
Receiver timeout mode
Single +5V power supply
Powers up to emulate SCC2692

Specifications

Part Life Cycle Code	Transferred	Reach Compliance Code
HTS Code	8542.31.00.01	JESD-30 Code	S-PQCC-J44
JESD-609 Code	e0	Number of Terminals	44
Operating Temperature-Max	85 °C	Operating Temperature-Min	-40 °C
Power Supplies	5 V	Qualification Status	Not Qualified
Supply Voltage-Nom	5 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	INDUSTRIAL
Terminal Finish	Tin/Lead (Sn/Pb)	Terminal Form	J BEND
Terminal Pitch	1.27 mm	Terminal Position	QUAD
uPs/uCs/Peripheral ICs Type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL