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SN65EPT22DGK +BOM

3.3-V dual LVTTL/LVCMOS to differential LVPECL buffer

SN65EPT22DGK General Description

Designed in an industry standard SOIC-8 package, the SN65EPT22DGK offers ease of integration and compatibility with existing systems. Additionally, the option for a TSSOP-8 package provides flexibility for different project requirements. This dual translator device is a valuable asset for engineers and designers looking to bridge the gap between LVTTL and LVPECL technologies

Texas Instruments, Inc Inventory

Key Features

  • Dual 3.3V LVTTL to LVPECL Buffer
  • Operating Range
    • LVPECL VCC = 3.0 V to 3.6 V With
      GND = 0 V
  • Support for Clock Frequencies to 2.0 GHz (typ)
  • 420 ps Typical Propagation Delay
  • Deterministic HIGH Output Value for Open Input
    Conditions
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100ELT23
  • PNP Single Ended Inputs for Minimal Loading
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion

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Texas Instruments, Inc Original Stock
Texas Instruments, Inc Inventory

Specifications

Function Driver, Translator Protocols LVPECL
Number of transmitters 2 Number of receivers 0
Supply voltage (V) 3.3 Signaling rate (MBits) 4000
Input signal CMOS, LVTTL Output signal LVPECL
Rating Catalog Operating temperature range (°C) -40 to 85
feature-logic-family feature-logic-function Translator
feature-translation LVCMOS/LVTTL to LVPECL feature-process-technology
feature-output-type feature-maximum-low-level-output-current-ma 50
feature-maximum-high-level-output-current-ma -50 feature-minimum-operating-supply-voltage-v 3
feature-maximum-operating-supply-voltage-v 3.6 feature-packaging Tube
feature-rad-hard feature-pin-count 8
feature-cecc-qualified No feature-esd-protection
feature-military No feature-aec-qualified No
feature-aec-qualified-number feature-auto-motive No
feature-p-pap No feature-eccn-code EAR99
feature-svhc Yes feature-svhc-exceeds-threshold No

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