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THC63LVD824 +BOM

Line Driver/Receiver, PQFP100

email Email: [email protected]
skype Skype: live:.cid.ab6b29428937b76
tel Tel: +852 95804164

Key Features

  • Wide dot clock range: 25-135MHz suited for VGA,
  • SVGA, XGA, SXGA, SXGA+ and UXGA
  • PLL requires No external components
  • Supports Dual Link, Dual-in (TTL)/Dual-out
  • (LVDS) pixel up to 170MHz dot clock for UXGA
  • Supports Single Link, Dual-in (TTL)/Single-out
  • (LVDS) pixel up to 135MHz dot clock for SXGA+
  • Supports Single Link, Single-in (TTL)/Single-out
  • (LVDS) pixel up to 85MHz dot clock for XGA
  • Clock edge selectable
  • Supports Reduced swing LVDS for Low EMI
  • Power down mode
  • Low power single 3.3V CMOS design
  • 100pin TQFP
  • THC63LVDM83R compatible

Specifications

Part Life Cycle Code Contact Manufacturer Reach Compliance Code compliant
ECCN Code EAR99 HTS Code 8542.39.00.01
JESD-30 Code S-PQFP-G100 JESD-609 Code e6
Moisture Sensitivity Level 3 Number of Terminals 100
Operating Temperature-Max 70 °C Operating Temperature-Min -10 °C
Power Supplies 3.3 V Qualification Status Not Qualified
Receive Delay-Max Supply Current-Max 173 mA
Supply Voltage-Nom 3.3 V Surface Mount YES
Temperature Grade COMMERCIAL Terminal Finish Tin/Bismuth (Sn/Bi)
Terminal Form GULL WING Terminal Pitch 0.5 mm
Terminal Position QUAD

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AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.

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