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See Technical Specifications

TL16C752CIRHBR +BOM

Dual UART With 64-Byte FIFO

Manufacturer:

Texas Instruments, Inc
Mfr.Part #:

TL16C752CIRHBR
Datasheet:

TL16C752CIRHBR Datasheet (PDF)
Number Of Channels:

2
FIFO (Byte):

64
Rx FIFO Trigger Levels (#):

16
Tx FIFO Trigger Levels (#):

16
EDA/CAD Models:

Request Free CAD Models for TL16C752CIRHBR

TL16C752CIRHBR General Description

The TL16C752CIRHBR is a highly advanced dual universal asynchronous receiver transmitter (UART) with multiple innovative features. With 64-byte FIFOs and data rates of up to 3 Mbps, this device offers exceptional performance for various communication applications. The presence of automatic hardware and software flow control ensures seamless data transmission with minimal errors. The transmission Character control register (TCR) simplifies the management of received FIFO threshold levels, enhancing the efficiency of data transfer processes

Key Features

SC16C752B and XR16M752 Pin Compatible With Additional Enhancements
Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
Characterized for Operation from –40°C to 85°C
Supports up to:
- 48-MHz Oscillator Input Clock (3 Mbps) for 5-V Operation
- 32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation
- 24-MHz Input Clock (1.5 Mbps) for 2.5-V Operation
- 16-MHz Input Clock (1 Mbps) for 1.8-V Operation
64-Byte Transmit/Receive FIFO
Software-Selectable Baud-Rate Generator
Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA, Interrupt Generation, and Software or Hardware Flow Control
Software/Hardware Flow Control
- Programmable Xon and Xoff Characters With Optional Xon Any Character
- Programmable Auto-RTS and Auto-CTS-Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)
DMA Signaling Capability for Both Received and Transmitted Data on PN Package
RS-485 Mode Support
Infrared Data Association (IrDA) Capability
Programmable Sleep Mode
Programmable Serial Interface Characteristics
- 5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2 Stop Bit Generation
- Even, Odd, or No Parity Bit Generation and Detection
False Start Bit and Line Break Detection
Internal Test and Loopback Capabilities

Specifications

Number of channels	2	FIFO (Byte)	64
Rx FIFO trigger levels (#)	16	Tx FIFO trigger levels (#)	16
Programmable FIFO trigger levels	Yes	CPU interface	X86
Baud rate at Vcc = 2.5 V & with 16x sampling (max) (MBps)	1.5	Baud rate at Vcc = 1.8 V & with 16x sampling (max) (MBps)	1
Baud rate at Vcc = 3.3 V & with 16x sampling (max) (MBps)	2	Baud rate at Vcc = 5 V & with 16x sampling (max) (MBps)	3
Operating voltage (V)	1.8, 2.5, 3.3, 5	Auto RTS/CTS	Yes
Rating	Catalog	Operating temperature range (°C)	-40 to 85, 0 to 70
feature-number-of-channels-per-chip	2	feature-transmit-fifo-byte	64
feature-receive-fifo-byte	64	feature-maximum-data-rate	3Mbps
feature-transmitter-and-receiver-fifo-counter	No	feature-standard-supported	RS-485
feature-minimum-operating-supply-voltage-v	1.62\|2.25\|3\|4.5	feature-maximum-operating-supply-voltage-v	1.98\|2.75\|3.6\|5.5
feature-maximum-supply-current-ma	4.5	feature-maximum-power-dissipation-mw
feature-packaging	Tape and Reel	feature-rad-hard
feature-pin-count	32	feature-cecc-qualified	No
feature-esd-protection		feature-military	No
feature-aec-qualified	No	feature-aec-qualified-number
feature-auto-motive	No	feature-p-pap	No
feature-eccn-code	EAR99	feature-svhc	No
feature-svhc-exceeds-threshold	No