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See Technical Specifications

UPD720102 +BOM

PRELIMINARYPRODUCTBRIEF,USB2.0HOSTCONTROLLER

Manufacturer:

NEC
Mfr.Part #:

UPD720102
Datasheet:

UPD720102 Datasheet (PDF)
Package/Case:

TQFP
RoHS:
EDA/CAD Models:

Request Free CAD Models for UPD720102

UPD720102 General Description

The μPD720102 complies with the universal serial bus specification revision 2.0 and open host controller interface specification for full-/low-speed signaling and Intel's enhanced host controller interface specification for high-speed signaling and works up to 480 Mbps. The μPD720102 is integrated 2 host controller cores with PCI interface and USB 2.0 transceivers into a single chip.

Key Features

Compliant with universal serial bus specification revision 2.0 (data rate: 1.5/12/480 Mbps)
Compliant with open host controller interface specification for USB release 1.0a
Compliant with enhanced host controller interface specification for USB revision 1.0
PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host controller core for high-speed signaling
Root hub with 3 (Max.) downstream facing ports which are shared by OHCI and EHCI host controller cores
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction
Supports hyper-speed transfer mode using HSMODE signal
32-bit 33 MHz host interface compliant with PCI specification revision 2.2
Supports PCI mobile design guide version 1.1
Supports PCI-bus power management interface specification revision 1.1
PCI bus bus-master access
Supports 3.3 V PCI
System clock is generated by 30 MHz crystal or 48 MHz clock input
Operational registers direct-mapped to PCI memory space
3.3 V single power supply, 1.5 V internal operating voltage from on chip regulator
On chip Rs and Rpd resistors for USB signals