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XC2S50E-6FTG256C +BOM

Family 50K Gates 1728 Cells 357MHz

Manufacturer:

XILINX
Mfr.Part #:

XC2S50E-6FTG256C
Datasheet:

XC2S50E-6FTG256C Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Obsolete
Pin Count:

256
ECCN Code:

EAR99
EDA/CAD Models:

Request Free CAD Models for XC2S50E-6FTG256C

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XC2S50E-6FTG256C General Description

The Spartan-II family of FPGAs has a reputation for reliability and efficiency, and the XC2S50E-6FTG256C upholds this standard with its impressive range of features. From communications systems to consumer electronics, this FPGA offers a versatile solution for implementing digital logic functions. Its compact size and robust design make it a top choice for engineers seeking a reliable and cost-effective solution for their application needs

Specifications

Pbfree Code	Yes	Part Life Cycle Code	Obsolete
Pin Count	256	Reach Compliance Code
ECCN Code	EAR99	HTS Code	8542.39.00.01
Additional Feature	MAXIMUM USABLE GATES = 50000	Clock Frequency-Max	357 MHz
Combinatorial Delay of a CLB-Max	0.47 ns	JESD-30 Code	S-PBGA-B256
JESD-609 Code	e1	Length	17 mm
Moisture Sensitivity Level	3	Number of CLBs	384
Number of Equivalent Gates	23000	Number of Inputs	182
Number of Logic Cells	1728	Number of Outputs	182
Number of Terminals	256	Operating Temperature-Max	85 °C
Operating Temperature-Min		Organization	384 CLBS, 23000 GATES
Peak Reflow Temperature (Cel)	260	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	2 mm
Supply Voltage-Max	1.89 V	Supply Voltage-Min	1.71 V
Supply Voltage-Nom	1.8 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	OTHER
Terminal Finish	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	Terminal Form	BALL
Terminal Pitch	1 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	30	Width	17 mm