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XC2V1000-4FG256I +BOM

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XC2V1000-4FG256I General Description

Featuring 96 Block RAM/FIFO (18 Kb each), this device offers ample storage for data-intensive tasks without compromising on speed. The 256-pin Fine-Pitch Ball Grid Array (FBGA) package provides high-density design capabilities while supporting various I/O standards, including LVDS, LVTTL, and HSTL. This versatility makes the XC2V1000-4FG256I suitable for a wide range of interface requirements

Specifications

Pbfree Code No Part Life Cycle Code Obsolete
Pin Count 256 Reach Compliance Code not_compliant
ECCN Code EAR99 HTS Code 8542.39.00.01
Clock Frequency-Max 650 MHz Combinatorial Delay of a CLB-Max 0.44 ns
JESD-30 Code S-PBGA-B256 JESD-609 Code e0
Length 17 mm Moisture Sensitivity Level 3
Number of CLBs 1280 Number of Equivalent Gates 1000000
Number of Inputs 172 Number of Logic Cells 11520
Number of Outputs 172 Number of Terminals 256
Organization 1280 CLBS, 1000000 GATES Peak Reflow Temperature (Cel) 225
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY Qualification Status Not Qualified
Seated Height-Max 2 mm Supply Voltage-Max 1.575 V
Supply Voltage-Min 1.425 V Supply Voltage-Nom 1.5 V
Surface Mount YES Technology CMOS
Terminal Finish Tin/Lead (Sn63Pb37) Terminal Form BALL
Terminal Pitch 1 mm Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 30 Width 17 mm

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