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750 MHz - Impressive processing speed for real-time applications
FBGA-676Manufacturer:
Mfr.Part #:
XC2V3000-5FG676I
Datasheet:
Pbfree Code:
No
Part Life Cycle Code:
Obsolete
Pin Count:
676
Reach Compliance Code:
not_compliant
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Lastly, the XC2V3000-5FG676I is designed for effortless programmability using Xilinx's design software tools, facilitating efficient development and testing of CPLD designs. With a focus on integration, flexibility, and exceptional performance capabilities, this CPLD is a reliable choice for engineers and designers looking to implement cutting-edge programmable logic designs
Pbfree Code | No | Part Life Cycle Code | Obsolete |
Pin Count | 676 | Reach Compliance Code | not_compliant |
ECCN Code | 3A991.D | HTS Code | 8542.39.00.01 |
Clock Frequency-Max | 750 MHz | Combinatorial Delay of a CLB-Max | 0.39 ns |
JESD-30 Code | S-PBGA-B676 | JESD-609 Code | e0 |
Length | 27 mm | Moisture Sensitivity Level | 3 |
Number of CLBs | 3584 | Number of Equivalent Gates | 3000000 |
Number of Inputs | 484 | Number of Logic Cells | 32256 |
Number of Outputs | 484 | Number of Terminals | 676 |
Organization | 3584 CLBS, 3000000 GATES | Peak Reflow Temperature (Cel) | 225 |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | Qualification Status | Not Qualified |
Seated Height-Max | 2.6 mm | Supply Voltage-Max | 1.575 V |
Supply Voltage-Min | 1.425 V | Supply Voltage-Nom | 1.5 V |
Surface Mount | YES | Technology | CMOS |
Terminal Finish | Tin/Lead (Sn63Pb37) | Terminal Form | BALL |
Terminal Pitch | 1 mm | Terminal Position | BOTTOM |
Time@Peak Reflow Temperature-Max (s) | 30 | Width | 27 mm |
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