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See Technical Specifications

XC2VP40-5FF1152I +BOM

XC2VP40-5FF1152I is a field programmable gate array with 6768 cells

Manufacturer:

XILINX
Mfr.Part #:

XC2VP40-5FF1152I
Datasheet:

XC2VP40-5FF1152I Datasheet (PDF)
Pbfree Code:

No
Part Life Cycle Code:

Obsolete
Pin Count:

1152
Reach Compliance Code:

not_compliant
EDA/CAD Models:

Request Free CAD Models for XC2VP40-5FF1152I

XC2VP40-5FF1152I General Description

Whether it's in telecommunications, high-performance computing, or image processing, the XC2VP40-5FF1152I shines in a multitude of industries. Its robust architecture and advanced functionalities make it a top choice for engineers and designers looking to push the boundaries of their designs. With Xilinx's Virtex-II Pro family pedigree, this FPGA delivers unparalleled performance and reliability

Specifications

Pbfree Code	No	Part Life Cycle Code	Obsolete
Pin Count	1152	Reach Compliance Code	not_compliant
ECCN Code	3A991.D	HTS Code	8542.39.00.01
Clock Frequency-Max	1050 MHz	Combinatorial Delay of a CLB-Max	0.36 ns
JESD-30 Code	S-PBGA-B1152	JESD-609 Code	e0
Length	35 mm	Moisture Sensitivity Level	4
Number of CLBs	4848	Number of Inputs	692
Number of Logic Cells	43632	Number of Outputs	644
Number of Terminals	1152	Organization	4848 CLBS
Peak Reflow Temperature (Cel)	225	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	3.4 mm
Supply Voltage-Max	1.575 V	Supply Voltage-Min	1.425 V
Supply Voltage-Nom	1.5 V	Surface Mount	YES
Technology	CMOS	Terminal Finish	TIN LEAD
Terminal Form	BALL	Terminal Pitch	1 mm
Terminal Position	BOTTOM	Time@Peak Reflow Temperature-Max (s)	30
Width	35 mm