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See Technical Specifications

XC4010E-4PC84I +BOM

This product features a 400-cell CMOS architecture in a PQCC84 plastic package, also known as a leadless chip carrier with 84 pins

Manufacturer:

XILINX INC
Mfr.Part #:

XC4010E-4PC84I
Datasheet:

XC4010E-4PC84I Datasheet (PDF)
Pbfree Code:

No
Part Life Cycle Code:

Obsolete
Pin Count:

84
HTS Code:

8542.39.00.01
EDA/CAD Models:

Request Free CAD Models for XC4010E-4PC84I

Email: [email protected]

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XC4010E-4PC84I General Description

Featuring a reprogrammable configuration memory and on-chip clock management resources, the XC4010E-4PC84I FPGA from Xilinx is designed to meet the needs of diverse digital design projects. With its 10,000 logic cells, 84 pins in a plastic quad flat pack (PQFP) package, and speed grade of 4, this FPGA delivers the performance and flexibility required for demanding applications. Its compatibility with design entry methods such as schematic capture and hardware description languages like VHDL or Verilog further enhances the usability of this advanced FPGA

Specifications

Pbfree Code	No	Part Life Cycle Code	Obsolete
Pin Count	84	Reach Compliance Code
HTS Code	8542.39.00.01	Additional Feature	MAX USABLE 10000 LOGIC GATES
Clock Frequency-Max	111 MHz	Combinatorial Delay of a CLB-Max	2.7 ns
JESD-30 Code	S-PQCC-J84	JESD-609 Code	e0
Length	29.3116 mm	Moisture Sensitivity Level	3
Number of CLBs	400	Number of Equivalent Gates	7000
Number of Inputs	160	Number of Logic Cells	400
Number of Outputs	160	Number of Terminals	84
Organization	400 CLBS, 7000 GATES	Peak Reflow Temperature (Cel)	225
Power Supplies	5 V	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	5.08 mm
Supply Voltage-Max	5.5 V	Supply Voltage-Min	4.5 V
Supply Voltage-Nom	5 V	Surface Mount	YES
Technology	CMOS	Terminal Finish	Tin/Lead (Sn85Pb15)
Terminal Form	J BEND	Terminal Pitch	1.27 mm
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	30
Width	29.3116 mm