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See Technical Specifications

XCV50-4PQ240C +BOM

The XCV50-4PQ240C FPGA comes in a 240-Pin PQFP package for easy integration

Manufacturer:

XILINX
Mfr.Part #:

XCV50-4PQ240C
Datasheet:

XCV50-4PQ240C Datasheet (PDF)
Pbfree Code:

No
Part Life Cycle Code:

Obsolete
Pin Count:

240
HTS Code:

8542.39.00.01
EDA/CAD Models:

Request Free CAD Models for XCV50-4PQ240C

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XCV50-4PQ240C General Description

Designers will appreciate the XCV50-4PQ240C's compatibility with the industry-standard JTAG interface for programming and configuration, ensuring seamless integration into existing workflows. Furthermore, the FPGA is supported by Xilinx's ISE software suite, providing a comprehensive toolset for design, simulation, and implementation. This combination of hardware and software support makes the XCV50-4PQ240C a compelling choice for designers seeking a reliable and efficient FPGA solution

Specifications

Pbfree Code	No	Part Life Cycle Code	Obsolete
Pin Count	240	Reach Compliance Code
HTS Code	8542.39.00.01	Clock Frequency-Max	250 MHz
Combinatorial Delay of a CLB-Max	0.8 ns	JESD-30 Code	S-PQFP-G240
JESD-609 Code	e0	Length	32 mm
Moisture Sensitivity Level	3	Number of CLBs	384
Number of Equivalent Gates	57906	Number of Inputs	166
Number of Logic Cells	1728	Number of Outputs	166
Number of Terminals	240	Operating Temperature-Max	85 °C
Operating Temperature-Min		Organization	384 CLBS, 57906 GATES
Peak Reflow Temperature (Cel)	225	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	4.1 mm
Supply Voltage-Max	2.625 V	Supply Voltage-Min	2.375 V
Supply Voltage-Nom	2.5 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	OTHER
Terminal Finish	Tin/Lead (Sn85Pb15)	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30	Width	32 mm