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See Technical Specifications

XCV600E-6HQ240I +BOM

This FPGA is designed for applications requiring advanced programmable logic capabilities and high-speed processing

Manufacturer:

XILINX
Mfr.Part #:

XCV600E-6HQ240I
Datasheet:

XCV600E-6HQ240I Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

240
HTS Code:

8542.39.00.01
Clock Frequency-Max:

357 MHz
EDA/CAD Models:

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XCV600E-6HQ240I General Description

Designed by Xilinx, the XCV600E-6HQ240I FPGA is a powerful field-programmable gate array from the Virtex-6 family. With 600,000 logic cells and various resources including configurable logic blocks, memory blocks, DSP slices, and I/O blocks, it caters to applications demanding high computational throughput. Its 240-pin package makes it suitable for telecommunications, networking, aerospace, and high-performance computing applications

Specifications

Part Life Cycle Code	Obsolete	Pin Count	240
Reach Compliance Code		HTS Code	8542.39.00.01
Clock Frequency-Max	357 MHz	Combinatorial Delay of a CLB-Max	0.47 ns
JESD-30 Code	S-PQFP-G240	JESD-609 Code	e0
Length	32 mm	Moisture Sensitivity Level	3
Number of CLBs	3456	Number of Equivalent Gates	186624
Number of Inputs	158	Number of Logic Cells	15552
Number of Outputs	158	Number of Terminals	240
Organization	3456 CLBS, 186624 GATES	Peak Reflow Temperature (Cel)	225
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	4.1 mm	Supply Voltage-Max	1.89 V
Supply Voltage-Min	1.71 V	Supply Voltage-Nom	1.8 V
Surface Mount	YES	Technology	CMOS
Terminal Finish	Tin/Lead (Sn85Pb15)	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30	Width	32 mm