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+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
TSSOP56Manufacturer:
Mfr.Part #:
DS90CF384MTDX/NOPB
Datasheet:
Function:
Deserializer
Color Depth (bps):
24
Input Compatibility:
FPD-Link LVDS
Pixel Clock Frequency (max) (MHz):
65
EDA/CAD Models:
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Incorporating advanced technology, this LVDS receiver delivers exceptional signal integrity and noise immunity for seamless data transmission. Easy to install and configure, the DS90CF384MTDX/NOPB offers a compact footprint without compromising on performance. The parallel interface simplifies connectivity, enabling seamless integration into existing systems
Function | Deserializer | Color depth (bps) | 24 |
Input compatibility | FPD-Link LVDS | Pixel clock frequency (max) (MHz) | 65 |
Output compatibility | LVCMOS | Features | Low-EMI Point-to-Point Communication |
EMI reduction | LVDS | Rating | Catalog |
Operating temperature range (°C) | -40 to 85 | feature-function | Receiver |
feature-number-of-drivers | 5 | feature-number-of-receivers | 4 |
feature-number-of-elements-per-chip | 4 | feature-transmission-data-rate-mbps | 1800 |
feature-maximum-propagation-delay-time-ns | feature-input-signal-type | LVDS | |
feature-differential-input-low-threshold-voltage-v | -0.1(Min) | feature-differential-input-high-threshold-voltage-v | 0.1(Max) |
feature-maximum-differential-output-voltage-v | 0.45 | feature-maximum-input-current-ua | 10 |
feature-supplier-temperature-grade | feature-packaging | Tape and Reel | |
feature-rad-hard | feature-pin-count | 56 | |
feature-cecc-qualified | No | feature-esd-protection | Yes |
feature-escc-qualified | feature-military | No | |
feature-aec-qualified | No | feature-aec-qualified-number | |
feature-eccn-code | EAR99 | feature-svhc | No |
feature-svhc-exceeds-threshold | No |
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