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EPC2LC20N +BOM

Configuration SRAM for FBGA

EPC2LC20N General Description

The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.

epc2lc20n epc2lc20n

Key Features

  • Easy-to-use 4-pin interface
  • Low current during configuration and near-zero standby mode current
  • EPC2 device has reprogrammable flash configuration memory
epc2lc20n epc2lc20n
epc2lc20n epc2lc20n

Specifications

Mount Surface Mount Number of Pins 20
Weight 722.005655 mg Frequency 16.7 MHz
Max Frequency 10 MHz Max Operating Temperature 70 °C
Max Supply Voltage 5.25 V Memory Size 256 kB
Memory Type FLASH Min Operating Temperature 0 °C
Min Supply Voltage 3 V Operating Supply Current 50 µA
Operating Supply Voltage 5 V Schedule B 8542320050
Height 3.81 mm Length 8.97 mm
Width 8.97 mm

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Ratings and Reviews

More
N
N**a 09/07/2023

Arrived well thank you

13
M
M**n 10/21/2020

Equipment in the photo. About working capacity later i will write. By delivery time-medium.

19
R
R**a 04/10/2020

Jim really knows the business. Has come through every time. Highly recommend

14

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