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H5TQ2G63DFR-11C +BOM

email Email: [email protected]
skype Skype: live:.cid.ab6b29428937b76
tel Tel: +852 95804164

Key Features

VDD=VDDQ=1.5V +/- 0.075V

Fully differential clock inputs (CK, CK) operation

Differential Data Strobe (DQS, DQS)

On chip DLL align DQ, DQS and DQS transition with CK

transition

DM masks write data-in at the both rising and falling

edges of the data strobe

All addresses and control inputs except data,

data strobes and data masks latched on the

rising edges of the clock

Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13

and 14 supported

Programmable additive latency 0, CL-1, and CL-2

supported

Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10

Programmable burst length 4/8 with both nibble

sequential and interleave mode

BL switch on the fly

8banks

Average Refresh Cycle (Tcase of0 oC~ 95oC)

- 7.8 s at 0oC ~ 85 oC

- 3.9 s at 85oC ~ 95 oC

JEDEC standard 78ball FBGA(x4/x8)

Driver strength selected by EMRS

Dynamic On Die Termination supported

Asynchronous RESET pin supported

ZQ calibration supported

TDQS (Termination Data Strobe) supported (x8 only)

Write Levelization supported

8 bit pre-fetch

This product in compliance with the RoHS directive.

Specifications

Product Category Memory ICs

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AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.

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In Stock: 6,007

Minimum Order: 1

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