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IS61LV256-15J +BOM

Ideal solution for embedded systems and industrial control applications

IS61LV256-15J General Description

DESCRIPTIONThe ISSI IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSIs high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns maximum.WhenCEis HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels.Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory.The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil DIP and SOJ, plus the 450-mil TSOP package.

Key Features

  • High-speed access time: 12, 15, 20, 25 ns
  • Automatic power-down when chip is deselected
  • CMOS low power operation
  • — 345 mW (max.) operating
  • — 7 mW (max.) CMOS standby
  • TTL compatible interface levels
  • Single 3.3V power supply
  • Fully static operation: no clock or refresh required
  • Three-state outputs

Specifications

Part Life Cycle Code Transferred Reach Compliance Code
ECCN Code EAR99 HTS Code 8542.32.00.41
Access Time-Max 15 ns I/O Type COMMON
JESD-30 Code R-PDSO-J28 JESD-609 Code e0
Memory Density 262144 bit Memory IC Type STANDARD SRAM
Memory Width 8 Number of Terminals 28
Number of Words 32768 words Number of Words Code 32000
Operating Mode ASYNCHRONOUS Operating Temperature-Max 70 °C
Operating Temperature-Min Organization 32KX8
Output Characteristics 3-STATE Parallel/Serial PARALLEL
Power Supplies 3.3 V Qualification Status Not Qualified
Standby Current-Max 0.002 A Standby Voltage-Min 3 V
Supply Current-Max 0.09 mA Supply Voltage-Nom (Vsup) 3.3 V
Surface Mount YES Technology CMOS
Temperature Grade COMMERCIAL Terminal Finish Tin/Lead (Sn/Pb)
Terminal Form J BEND Terminal Pitch 1.27 mm
Terminal Position DUAL

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