Payment Method
![hsbc](/img/service-policies-hsbc.png)
![paypal](/img/service-policies-paypal.png)
![wu](/img/service-policies-wu.png)
![mg](/img/service-policies-mg.png)
Transform your system architecture with this versatile and programmable crosspoint integrated circuit
TapeCyeManufacturer:
Mfr.Part #:
ispGDX240VA-7BN388I
Datasheet:
Series:
ispGDX®
Type:
Crosspoint Switch
Circuit:
1 x 240:240
Independent Circuits:
1
Please fill in the short form below and we will provide you the quotation immediately.
The ispGDXV/VA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including:
• Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces
The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns.
The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN = 0.
Category | Integrated Circuits (ICs)LogicSignal Switches, Multiplexers, Decoders | Series | ispGDX® |
Type | Crosspoint Switch | Circuit | 1 x 240:240 |
Independent Circuits | 1 | Current - Output High, Low | 12mA, 24mA |
Voltage Supply Source | Single Supply | Voltage - Supply | 3V ~ 3.6V |
Operating Temperature | -40°C ~ 85°C (TA) | Mounting Type | Surface Mount |
Base Product Number | ISPGDX240 |
After-Sales & Settlement Related
Payment Method
For alternative payment channels, please reach out to us at:
[email protected]Shipping Method
AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.
365-Day Product
Quality Guarantee
We promise to provide 365 days quality assurance service for all our products.
Qty. | Unit Price | Ext. Price |
---|---|---|
1+ | - | - |
The prices below are for reference only.
All bill of materials (BOM) can be sent via email to
[email protected],
or fill below form to Quote for ispGDX240VA-7BN388I, guaranteed quotes back within
12hr.
GAL16V8D-25LPN
LATTICE SEMICONDUCTOR CORP
Fast EE PLD with 25ns performance
PALCE20V8H-25PC/4
lattice
PAL-type CMOS integrated circuit
PALCE610H-25PC
lattice
With the PALCE610H-25PC, users can quickly and easily implement custom logic solutions for their projects
5962-8983904RA
lattice
This advanced PLD product, numbered 5962-8983904RA, combines the latest EE technology with a PAL-type architecture
GAL16V8D-15LJ
LATTICE SEMICONDUCTOR CORP
20-Pin PLCC package for easy integration