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See Technical Specifications

LC4256V-10TN100I +BOM

ispMACH4000 Series 256 MacroCell 64 I/O 3.6V SuperFAST High CPLD

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

The features of LC4256V-10TN100I include enhanced ORP information in device pinout tables consistent with the ORP Combinations for I/O Blocks tables
corrected GLB/MC/Pad information in the 256-fpBGA pinouts
and support for lead-free packaging

The applications of LC4256V-10TN100I include general purpose I/O used by the logic array
and it is part of the ispMACH 4000 Family

Pbfree Code	Yes	Part Life Cycle Code	Active
Pin Count	100	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
Architecture	PAD-TYPE	Clock Frequency-Max	86 MHz
In-System Programmable	YES	JESD-30 Code	S-PQFP-G100
JESD-609 Code	e3	JTAG BST	YES
Length	14 mm	Moisture Sensitivity Level	3
Number of Dedicated Inputs	10	Number of I/O Lines	64
Number of Inputs	74	Number of Macro Cells	256
Number of Outputs	64	Number of Product Terms	83
Number of Terminals	100	Operating Temperature-Max	105 °C
Operating Temperature-Min	-40 °C	Organization	10 DEDICATED INPUTS, 64 I/O
Output Function	MACROCELL	Peak Reflow Temperature (Cel)	260
Programmable Logic Type	EE PLD	Propagation Delay	10 ns
Qualification Status	Not Qualified	Seated Height-Max	1.6 mm
Supply Voltage-Max	3.6 V	Supply Voltage-Min	3 V
Supply Voltage-Nom	3.3 V	Surface Mount	YES
Terminal Finish	MATTE TIN	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	40	Width	14 mm