This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Images are for reference only,

See Technical Specifications

LCMXO2-1200HC-4TG100CR1 +BOM

Small, versatile FPGA

Manufacturer:

LATTICE SEMICONDUCTOR CORP
Mfr.Part #:

LCMXO2-1200HC-4TG100CR1
Datasheet:

LCMXO2-1200HC-4TG100CR1 Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

100
HTS Code:

8542.39.00.01
Clock Frequency-Max:

133 MHz
EDA/CAD Models:

Request Free CAD Models for LCMXO2-1200HC-4TG100CR1

LCMXO2-1200HC-4TG100CR1 General Description

Designed for space-constrained applications, the LCMXO2-1200HC-4TG100CR1 comes in a compact 100-pin TQFP package. Its built-in security features ensure the protection of design IP and data, providing peace of mind for users. Additionally, the device's support for low-power operation makes it an ideal choice for battery-powered applications, offering energy efficiency without compromising on performance

Key Features

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
–PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

LATTICE SEMICONDUCTOR CORP Original Stock

Specifications

Part Life Cycle Code	Obsolete	Pin Count	100
Reach Compliance Code		HTS Code	8542.39.00.01
Clock Frequency-Max	133 MHz	JESD-30 Code	S-PQFP-G100
JESD-609 Code	e3	Moisture Sensitivity Level	3
Number of Inputs	80	Number of Logic Cells	1280
Number of Outputs	80	Number of Terminals	100
Operating Temperature-Max	85 °C	Operating Temperature-Min
Peak Reflow Temperature (Cel)	260	Power Supplies	2.5/3.3 V
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Supply Voltage-Max	3.465 V	Supply Voltage-Min	2.375 V
Supply Voltage-Nom	2.5 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	OTHER
Terminal Finish	Matte Tin (Sn)	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30