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See Technical Specifications

MC100LVEP14DTR2G +BOM

With a PDSO20 package, the MC100LVEP14DTR2G clock driver offers 5 true outputs and 0 inverted outputs for precise clock signal distribution

Manufacturer:

ON
Mfr.Part #:

MC100LVEP14DTR2G
Datasheet:

MC100LVEP14DTR2G Datasheet (PDF)
Compliance:

PbAHP
Case Outline:

9.48
MSL Type:

1
MSL Temp (°C):

260
EDA/CAD Models:

Request Free CAD Models for MC100LVEP14DTR2G

MC100LVEP14DTR2G General Description

The MC100LVEP14DTR2G is suitable for ECL/PECL input signals, whether they are differential or single-ended. The inclusion of an VBB output allows for the use of HSTL inputs when operating under PECL conditions, making this driver adaptable to a range of signaling requirements. This level of flexibility ensures that the MC100LVEP14DTR2G can accommodate different input signal types, making it an ideal choice for a wide range of clock distribution needs

Key Features

A high-speed LVPECL-to-LVDS converter
With a typical input sensitivity of 2mVpp
The device features a high common-mode rejection ratio and low noise

Application

Performance computing
Data transmission speed
Networking applications

Specifications

Status	Active	Compliance	PbAHP
Case Outline	9.48	MSL Type	1
MSL Temp (°C)	260	Container Type	REEL
Container Qty.	2500	ON Target	Y
Type	Buffer	Channels	1
Input / Output Ratio	2:1:5	Input Level	LVDS
Output Level	ECL	VCC Typ (V)	3.3
tJitterRMS Typ (ps)	0.181	tskew(o-o) Max (ps)	25
tpd Typ (ns)	0.4	tR & tF Max (ps)	225
fmaxClock Typ (MHz)	2000	Pricing ($/Unit)	Price N/A