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MT48LC2M32B2TG-6 +BOM

SDRAM with 2M x 32 capacity and 86-pin plastic TSSOP package

Key Features

  • PC100 functionality
  • Fully synchronous; all signals registered on positive edge of system clock
  • Internal pipelined operation; column address can be changed every clock cycle
  • Internal banks for hiding row access/precharge
  • Programmable burst lengths: 1, 2, 4, 8, or full page
  • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
  • Self Refresh Mode
  • 64ms, 4,096-cycle refresh (15.6µs/row)
  • LVTTL-compatible inputs and outputs
  • Single +3.3V ±0.3V power supply
  • Supports CAS latency of 1, 2, and 3

Specifications

ECCN (US) EAR99 Part Status Obsolete
HTS 8542.32.00.71 Automotive No
PPAP No DRAM Type SDR SDRAM
Chip Density (bit) 64M Organization 2Mx32
Number of Internal Banks 4 Number of Words per Bank 512K
Number of Bits/Word (bit) 32 Data Bus Width (bit) 32
Maximum Clock Rate (MHz) 166 Maximum Access Time (ns) 17|7.5|5.5
Address Bus Width (bit) 13 Interface Type LVTTL
Minimum Operating Supply Voltage (V) 3 Maximum Operating Supply Voltage (V) 3.6
Operating Current (mA) 180 Minimum Operating Temperature (°C) 0
Maximum Operating Temperature (°C) 70 Supplier Temperature Grade Commercial
Number of I/O Lines (bit) 32 Packaging Tray
Mounting Surface Mount PCB changed 86
Pin Count 86 Lead Shape Gull-wing

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