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P89C51RC2BA +BOM

CMOS technology

Key Features

  • 80C51 Central Processing Unit
  • On-chip Flash Program Memory with In-System Programming
  • (ISP) and In-Application Programming (IAP) capability
  • Boot ROM contains low level Flash programming routines for downloading via the UART
  • Can be programmed by the end-user application (IAP)
  • 6 clocks per machine cycle operation (standard)
  • 12 clocks per machine cycle operation (optional)
  • Speed up to 20 MHz with 6 clock cycles per machine cycle
  • (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle
  • Fully static operation
  • RAM expandable externally to 64 kB
  • 4 level priority interrupt
  • 8 interrupt sources
  • Four 8-bit I/O ports
  • Full-duplex enhanced UART
  • – Framing error detection
  • – Automatic address recognition
  • Power control modes
  • – Clock can be stopped and resumed
  • – Idle mode
  • – Power down mode
  • Programmable clock out
  • Second DPTR register
  • Asynchronous port reset
  • Low EMI (inhibit ALE)
  • Programmable Counter Array (PCA)
  • – PWM
  • – Capture/compare

Specifications

Part Life Cycle Code Transferred Reach Compliance Code not_compliant
HTS Code 8542.31.00.01 Bit Size 8
CPU Family 8051 JESD-30 Code S-PQCC-J44
JESD-609 Code e0 Number of Terminals 44
Operating Temperature-Max 70 °C Operating Temperature-Min
Power Supplies 5 V Qualification Status Not Qualified
RAM (bytes) 512 ROM (words) 32768
ROM Programmability FLASH Speed 33 MHz
Supply Voltage-Nom 5 V Surface Mount YES
Technology CMOS Temperature Grade COMMERCIAL
Terminal Finish Tin/Lead (Sn85Pb15) Terminal Form J BEND
Terminal Pitch 1.27 mm Terminal Position QUAD

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