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See Technical Specifications

W971GG6SB25I +BOM

64 Megabytes x 16

Manufacturer:

Winbond Electronics
Mfr.Part #:

W971GG6SB25I
Datasheet:

W971GG6SB25I Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Reach Compliance Code:

compliant
ECCN Code:

EAR99
HTS Code:

8542.32.00.32
EDA/CAD Models:

Request Free CAD Models for W971GG6SB25I

Email: [email protected]

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Tel: +852 95804164

W971GG6SB25I General Description

The W971GG6SB25I is a cutting-edge SDRAM module that offers incredible speed and reliability for a wide range of electronic devices. With a capacity of 1GB and operating at an impressive 2666MHz, this module ensures seamless performance in computers, laptops, and servers. The inclusion of a 96-bit SPD EEPROM allows for hassle-free recognition and configuration of memory settings, enhancing user convenience

Key Features

Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to
both edges of DQS
Posted CAS programmable additive latency supported to make command and
data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for
better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8x12.5 mm2), using Lead free materials with RoHS compliant

Specifications

Part Life Cycle Code	Obsolete	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.32.00.32
Access Mode	MULTI BANK PAGE BURST	Access Time-Max	0.4 ns
Additional Feature	AUTO/SELF REFRESH	JESD-30 Code	R-PBGA-B84
Length	12.5 mm	Memory Density	1073741824 bit
Memory IC Type	DDR DRAM	Memory Width	16
Number of Functions	1	Number of Ports	1
Number of Terminals	84	Number of Words	67108864 words
Number of Words Code	64000000	Operating Mode	SYNCHRONOUS
Organization	64MX16	Peak Reflow Temperature (Cel)	NOT SPECIFIED
Seated Height-Max	1.2 mm	Self Refresh	YES
Supply Voltage-Max (Vsup)	1.9 V	Supply Voltage-Min (Vsup)	1.7 V
Supply Voltage-Nom (Vsup)	1.8 V	Surface Mount	YES
Technology	CMOS	Terminal Form	BALL
Terminal Pitch	0.8 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED	Width	8 mm