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K4X2G323PD-8GD8 +BOM

DRAM Chip Mobile-DDR SDRAM 2Gbit 64Mx32 1.8V 90-Pin FBGA

email Email: [email protected]
skype Skype: live:.cid.ab6b29428937b76
tel Tel: +852 95804164

Key Features

  • 1.8V power supply, 1.8V I/O power
  • Double-data-rate architecture; two data transfers per clock cycle
  • Bidirectional data strobe(DQS)
  • Four banks operation
  • Differential clock inputs(CK and CK)
  • MRS cycle with address key programs
  • - CAS Latency ( 2, 3 )
  • - Burst Length ( 2, 4, 8, 16 )
  • - Burst Type (Sequential & Interleave)
  • - Partial Self Refresh Type ( Full, 1/2, 1/4 Array )
  • - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
  • Internal Temperature Compensated Self Refresh
  • Deep Power Down Mode
  • All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
  • Data I/O transactions on both edges of data strobe, DM for masking.
  • Edge aligned data output, center aligned data input.
  • No DLL; CK to DQS is not synchronized.
  • LDM/UDM for write masking only.
  • Auto refresh duty cycle
  • - 7.8us for -25 to 85 °C

Specifications

ECCN EAR99 Automotive No
Supplier Cage Code 1542F

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