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See Technical Specifications

ZL30364GDG2 +BOM

Synchronous Ethernet and IEEE compliant for reliable transmissio

Manufacturer:

Microchip Technology
Mfr.Part #:

ZL30364GDG2
Datasheet:

ZL30364GDG2 Datasheet (PDF)
Programmabe:

Not Verified
PLL:

Yes
Main Purpose:

Ethernet, Fibre Channel, SONET/SDH, Stratum
Input:

Clock
EDA/CAD Models:

Request Free CAD Models for ZL30364GDG2

ZL30364GDG2 General Description

The ZL30364GDG2 is a cutting-edge clock generator and jitter attenuator IC designed for high-speed communication applications. Its advanced features include integrated digital PLLs for on-the-fly frequency changes and fast lock times, as well as programmable output skew and phase adjustment capabilities for precise timing alignment within the system. With its ability to generate multiple output clocks with low jitter and phase noise, this device is perfect for applications that require accurate timing synchronization

Key Features

Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
Supports the requirements of Telcordia GR-1244
Stratum 3 and GR-253, ITU-T G.813, and G.781
Supports ITU-T G.823, G.824 and G.8261 for 2048
kbit/s and 1544 kbit/s interfaces
Meets the SONET/SDH jitter generation
requirements up to OC-48/STM-16
Synchronizes to telecom reference clocks (2 kHz,
N8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
Supports composite clock inputs (64 kHz, 64 kHz +
8 kHz, 64kHz + 8 kHz + 400 Hz)
Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Gigabit Ethernet PHYs
Programmable output synthesizers (P0, P1)
generate telecom clock frequencies from any
multiple of 8 kHz up to 100 MHz
Generates several styles of telecom frame pulses
with selectable pulse width, polarity and frequency
Provides two DPLLs which are independently
configurable through a serial interface
Internal state machine automatically controls
mode of operation (free-run, locked, holdover)
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Provides automatic reference switching and
holdover during loss of reference input
Supports master/slave configuration and dynamic
input to output delay compensation for
AdvancedTCA™
Configurable input to output delay and output to
output phase alignment

Application

ITU-T G.8262 System Timing Cards which support
1 GbE and 10 GbE interfaces
Telcordia GR-253 Carrier Grade SONET/SDH
Stratum 3 System Timing Cards
System Timing Cards which supports ITU-T G.781
SETS (SDH Equipment Timing Source)

Specifications

Programmabe	Not Verified	PLL	Yes
Main Purpose	Ethernet, Fibre Channel, SONET/SDH, Stratum	Input	Clock
Output	LVCMOS, LVPECL	Number of Circuits	1
Ratio - Input:Output	11:16	Differential - Input:Output	Yes/Yes
Frequency - Max	750MHz	Operating Temperature	-40°C ~ 85°C
Mounting Type	Surface Mount	Base Product Number	ZL30364