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See Technical Specifications

SI5515DC-T1-E3 +BOM

Dual N & P Channel 20 V 0.04 Ohms Surface Mount Power Mosfet - 1206-8 ChipFET

Manufacturer:

VISHAY
Mfr.Part #:

SI5515DC-T1-E3
Datasheet:

SI5515DC-T1-E3 Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Obsolete
Pin Count:

8
ECCN Code:

EAR99

SI5515DC-T1-E3 General Description

Featuring both N and P channel transistors, the SI5515DC-T1-E3 provides versatility in circuit design. The threshold voltage (Vgs typ) of 400mV ensures precise control over the switching characteristics of the MOSFET. This makes it ideal for use in power management circuits, battery protection systems, and other applications requiring efficient power switching

Key Features

SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 24000 PLD Gates / 512 Macrocells
— Up to 288 I/O Pins
— 512 Registers
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 110 MHz Maximum Operating Frequency
— tpd = 8.5 ns Propagation Delay
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns, tsu3 (CLK2/3) = 3.5ns
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O™) Supports Programmable Bus Hold, Pull-up, Open Drain and Slew and Skew Rate Options
— Six Global Output Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell
ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms

Specifications

Pbfree Code	Yes	Part Life Cycle Code	Obsolete
Pin Count	8	Reach Compliance Code
ECCN Code	EAR99	Additional Feature	ULTRA-LOW RESISTANCE
Configuration	SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE	DS Breakdown Voltage-Min	20 V
Drain Current-Max (ID)	4.4 A	Drain-source On Resistance-Max	0.04 Ω
FET Technology	METAL-OXIDE SEMICONDUCTOR	JESD-30 Code	R-PDSO-C8
JESD-609 Code	e3	Moisture Sensitivity Level	1
Number of Elements	2	Number of Terminals	8
Operating Mode	ENHANCEMENT MODE	Operating Temperature-Max	150 °C
Polarity/Channel Type	N-CHANNEL AND P-CHANNEL	Power Dissipation-Max (Abs)	1.1 W
Qualification Status	Not Qualified	Surface Mount	YES
Terminal Finish	MATTE TIN	Terminal Form	C BEND
Terminal Position	DUAL	Transistor Application	SWITCHING
Transistor Element Material	SILICON