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See Technical Specifications

H5TC2G63GFR-PBA +BOM

Low-power CMOS memory solution for PBGA applications

Manufacturer:

Sk Hynix
Mfr.Part #:

H5TC2G63GFR-PBA
Datasheet:

H5TC2G63GFR-PBA Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Reach Compliance Code:

compliant
ECCN Code:

EAR99
HTS Code:

8542.32.00.36
EDA/CAD Models:

Request Free CAD Models for H5TC2G63GFR-PBA

Application

SK Hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Specifications

Part Life Cycle Code	Obsolete	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.32.00.36
Date Of Intro	2016-06-15	Access Mode	MULTI BANK PAGE BURST
Additional Feature	AUTO/SELF REFRESH	JESD-30 Code	R-PBGA-B96
Length	13 mm	Memory Density	2147483648 bit
Memory IC Type	DDR DRAM	Memory Width	16
Number of Functions	1	Number of Ports	1
Number of Terminals	96	Number of Words	134217728 words
Number of Words Code	128000000	Operating Mode	SYNCHRONOUS
Operating Temperature-Max	85 °C	Organization	128MX16
Peak Reflow Temperature (Cel)	NOT SPECIFIED	Seated Height-Max	1.2 mm
Self Refresh	YES	Supply Voltage-Max (Vsup)	1.45 V
Supply Voltage-Min (Vsup)	1.283 V	Supply Voltage-Nom (Vsup)	1.35 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	OTHER	Terminal Form	BALL
Terminal Pitch	0.8 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED	Width	7.5 mm