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M2050-11I693.4830T +BOM
SAW PLL For 10GBE 64B/66B FEC
36-CLCC-
Manufacturer:
Renesas Electronics Corporation
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Mfr.Part #:
M2050-11I693.4830T
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Datasheet:
-
Programmabe:
Not Verified
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PLL:
Yes
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Input:
LVCMOS, LVDS, LVPECL, LVTTL
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Output:
LVPECL
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M2050-11I693.4830T General Description
The M2050/51/52/53 is a VCSO (Voltage Controlled SAW Oscillator) based clock PLL designed for FEC clock ratio translation in 10Gb optical systems such as 10GbE 64b/66b. It supports both mapping and de-mapping of 64b/66b encoding and FEC (Forward Error Correction) clock multiplication ratios. The ratios are pin-selected from pre-programming look-up tables.
Key Features
- Integrated SAW delay line
- Output of 15 to 700 MHz
- Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50Hz to 80MHz)
- Pin-selectable PLL divider ratios support 64b/66b and FEC encoding/decoding ratios:
- M2050: Map 10GbE to LAN, 255/238 FEC, or 255/237 FEC
- M2051: De-map 10GbE LAN or 255/238 FEC to 10GbE
- M2052: De-map 255/237 FEC & 255/238 FEC to 10GbE LAN
- Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance
- LVPECL clock output (CML and LVDS options available)
- Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
- Loss of Lock (LOL) output pin
- Narrow Bandwidth control input (NBW Pin)
- Hitless Switching (HS) options with or without Phase Build-out (PBO) available
- performance conforms with SONET (GR-253) /SDH (G.813) MTIE and TDEV during reference clock reselection
- Single 3.3V power supply
- Small 9 x 9 mm SMT (surface mount) package
Specifications
Series | - | Programmabe | Not Verified |
PLL | Yes | Input | LVCMOS, LVDS, LVPECL, LVTTL |
Output | LVPECL | Number of Circuits | 1 |
Ratio - Input:Output | 2:2 | Differential - Input:Output | Yes/Yes |
Frequency - Max | 693.483MHz | Divider/Multiplier | Yes/No |
Voltage - Supply | 3.3V | Operating Temperature | -40°C ~ 85°C |
Mounting Type | Surface Mount | Base Product Number | M2050-11 |
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In Stock: 7,696
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