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See Technical Specifications

M2061-11-622.0800T +BOM

VCSO FEC PLL For SONET/OTN

Manufacturer:

Renesas Electronics Corporation
Mfr.Part #:

M2061-11-622.0800T
Datasheet:

M2061-11-622.0800T Datasheet (PDF)
Programmabe:

Not Verified
PLL:

Yes
Input:

LVCMOS, LVDS, LVPECL
Output:

LVPECL

M2061-11-622.0800T General Description

The M2060/61/62 and M2065/66/67 are VCSO (Voltage Controlled SAW Oscillator) based clock PLLs designed for FEC clock ratio translation in 10Gb optical systems such as OC-192 or 10GbE. They support FEC (Forward Error Correction) clock multiplication ratios, both forward (mapping) and inverse (de-mapping). Multiplication ratios are pin-selected from pre-programming look-up tables.

Key Features

Integrated SAW delay line
Output of 15 to 700 MHz
Low phase jitter
Pin-selectable PLL divider ratios support FEC ratios
M2060/65: OTU1 (255/238) and OTU2 (255/237) Mapping
M2061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping
M2062/67: OTU1 (238/255) and OTU2 (237/255) De-mapping
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin
Narrow Bandwidth control input (NBW pin) to adjust loop bandwidth
Hitless Switching (HS) options with or without Phase Build-out (PBO) available to enable SONET (GR-253) /SDH (G.813) MTIE and TDEV compliance during reference clock reselection
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package

Specifications

Series	-	Programmabe	Not Verified
PLL	Yes	Input	LVCMOS, LVDS, LVPECL
Output	LVPECL	Number of Circuits	1
Ratio - Input:Output	2:2	Differential - Input:Output	Yes/Yes
Frequency - Max	622.08MHz	Divider/Multiplier	Yes/No
Voltage - Supply	3.3V	Operating Temperature	0°C ~ 70°C
Mounting Type	Surface Mount	Base Product Number	M2061-11